1. Field of the Invention
Example embodiments of the present invention relate in general to a heat-radiating semiconductor chip, a tape wiring substrate and a tape package using the same.
2. Description of the Related Art
With the development of the flat display industry, for example liquid crystal displays (LCD) for portable phones, thin-film transistor (TFT/LCDs) for computers and plasma display panels (PDPs) for domestic use, tape packages as a component of flat display devices have been developing. As the flat display devices move towards smaller sizes, the tape packages accordingly require a finer pitch of its wiring patterns.
The tape packages use a tape wiring substrate and include tape carrier packages (TCPs) and chip on film (COF) packages. The TCPs include a tape wiring substrate with a window and a semiconductor chip mounted on the tape wiring substrate using an inner lead bonding (ILB) method. The COF packages may include a solid tape wiring substrate and a semiconductor chip mounted on the tape wiring substrate using a flip chip bonding process.
In the COF packages, input and output terminal patterns act as external connection terminals instead of solder balls. The input and output terminal patterns are directly attached to a printed circuit board or a display panel.
FIG. 1 is a plan view of a conventional tape package 100; FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1; FIG. 3 is a plan view of a semiconductor chip 10 of the tape package 100 in FIG. 1.
Referring to FIGS. 1 to 3, the COF package 100 includes a tape wiring substrate 20 and the semiconductor chip 10 flip chip bonded to the tape wiring substrate 20 via bumps 18. An encapsulant 30 seals a flip chip bonded portion through an underfill process. The bumps 18 connect the semiconductor chip 10 to input and output wiring patterns 23 and 28 of the tape wiring substrate 20.
The semiconductor chip 10 includes input pads 12 and output pads 16 along the edges of an active surface 11. Logic cells are provided in a central area of the active surface 11. The input pads 12 are arranged along one longer side of the semiconductor chip 10. The input pads 12 include a plurality of signal pads 13, power pads 14 and ground pads 15. The power pads 14 and ground pads 15 are arranged so that power and ground is uniformly provided over the semiconductor chip 10.
FIG. 4 is a temperature distribution diagram of heat occurring during operation of the tape package 100 of FIG. 1. Referring to FIG. 4, a majority of heat is generated from the central area of the semiconductor chip 10 where the logic cells are located. The heat is radiated to a printed circuit board 40 and a panel 50 through the input and output wiring patterns 23 and 28 connected to the semiconductor chip 10.
The input and output wiring patterns 23 and 28 are formed at a uniform pitch and a uniform width, regardless of the route of heat, thereby resulting in inefficient heat radiation. The dispersed arrangement of the power pads 14 and ground pads 15 can result in an increased length of the input wiring patterns 23, which could reduce the heat radiation capability of the tape package 100. Generally, the input wiring patterns 23 which are arranged in a peripheral area of the semiconductor chip 10 are longer than those input wiring patterns 23 arranged in a central area of the semiconductor chip 10. Therefore, the input wiring patterns 23 on the periphery that are connected to the power pads 14 and ground pads 15 have a longer length than those arranged at the central area of the semiconductor chip 10. As a result, the route of heat through the input wiring patterns 23 connected to the power pads 14 and ground pads 15 may be increased in an effort to reduce the heat radiation capability. Further, as the frequency and voltage of the semiconductor chip 10 increases, more heat is generated from the semiconductor chip 10.